The present invention relates to an arithmetic circuit and, more particularly, to an arithmetic circuit for executing matrix multiplication.
FIG. 3 shows a conventional arithmetic circuit for consecutively executing matrix multiplication twice. Output ports DO of first and second memories 13 and 14 in which matrices X and Y are respectively stored are respectively connected to first and second input ports IA and IB of a first multiplier 9. An output port DO of a third memory 15 in which a matrix Z is stored is connected to a first input port IA of a second multiplier 11. Output ports Al, A2, A3, and A4 of an address generator 17 are respectively connected to address input ports A1 of the fourth, second, first, and third memories 16, 14, 13, and 15. An output port OZ of the first multiplier 9 is connected to an input port IX of a first accumulator 10. An output port OY of the first accumulator 10 is connected to an input port DI of the fourth memory 16. An output port Do of the fourth memory 16 is connected to a second input port IB of the second multiplier 11. An output port OZ of the second multiplier 11 is connected to an input port IX of a second accumulator 12. An output OY of the second accumulator 12 is connected to an output terminal 18.
Such an arithmetic circuit is designed to perform multiplication based on the matrices X, Y, and Z in the following manner. Elements of the matrices X and Y are respectively read out from the first and second memories 13 and 14, and a multiplication of X.times.Y is performed by using the first multiplier 9 and the first accumulator 10. The product of X.times.Y is then written in the fourth memory 16. In addition, an element of the matrix Z and elements of the product of X.times.Y are respectively read out from the third and fourth memories 15 and 16, and a multiplication of (X.times.Y).times.Z is performed by the second multiplier 11 and the second accumulator 12, thus executing matrix multiplication twice. This calculation method will be described in detail below.
Assume that the matrices X, Y, and Z are N.times.N matrices and are respectively constituted by elements given by following equations (1) to (3): ##EQU1##
In this case, each matrix element as a matrix multiplication result is represented by equation (4): ##EQU2## where (n-1).gtoreq.l and m (integer).gtoreq.0.
If the product of X.times.Y is X', the second multiplication is: ##EQU3##
In the prior art, two consecutive matrix multiplications are performed by independently operating equations (4) and (5). The arithmetic circuit is designed to perform such calculations in the following manner. The calculation result of equation (4) obtained by the first multiplier 9 and the first accumulator 10 is temporarily stored in the fourth memory 16. Thereafter, the calculation result of equation (4) read out from the fourth memory 16 and the matrix Z read out from the third memory 15 are operated on the basis of equation (5).
In the above-described conventional arithmetic circuit, however, since two matrix multiplications are independently executed, a memory for storing an intermediate product of (X.times.Y) is required. In addition, since multipliers and accumulators are required in pairs, the number of elements and power consumption are increased. Therefore, in a semiconductor IC, the chip area is undesirably increased. Furthermore, unless calculation of a matrix element of the first matrix multiplication (X.times.Y) is completed, the second multiplication cannot be started, the operation time is undesirably prolonged.